1. Field of the Invention
The disclosure relates generally to a semiconductor device using a level shift circuit, and a level shift circuit having a latch used in a semiconductor device, such as a NAND type flash memory.
2. Description of the Related Art
In semiconductor devices such as a NAND flash memory, for the requirement of versatility, one semiconductor device (chip device) is designed for operation with some external power supply voltages, such as 3.3V and 1.8V.
FIG. 22 is a block diagram illustrating a power supply voltage usage state of each circuit when the external power supply voltage VCC=3.3V is applied to the flash memory of the prior art. In addition, FIG. 23 is a block diagram illustrating a power supply voltage usage state of each circuit when the external power supply voltage VCC=1.8V is applied to the flash memory of the prior art. In FIGS. 22 and 23, the NAND type flash memory consists of a cell array 1, a page buffer 2, a row decoder 3, a power supply circuit 4 (a high voltage HV, a middle voltage MV), a power supply circuit 5 (a reference voltage Vref and a low voltage LV), a control logic 6, a buffer and latch, etc. 7, an input/output buffer 8, and an input signal buffer 9.
FIGS. 22 and 23 are the same NAND type flash memory, but different external power supply voltages VCC are applied thereto, and the power supply voltage usage state of each circuit are different. In the embodiment of FIG. 22, the internal power supply voltage VDD in the input/output buffer 8 and the input signal buffer 9 is 3.3V, the internal power supply voltage VDD in a part of page buffer 2, a part of the row decoder 3, the control logic 6 and the buffer and latch, etc. 7 is 1.9V, the internal power supply voltage VDD in another part of page buffer 2, another part of the row decoder 3 and the power supply circuit 4 is 5V. In the embodiment of FIG. 23, the internal power supply voltage VDD in a part of page buffer 2, a part of the row decoder 3, the control logic 6 and the buffer and latch, etc. 7 is 1.8V, and the internal power supply voltage VDD in another part of page buffer 2, another part of the row decoder 3, the power supply circuit 4 the input/output buffer 8 and the input signal buffer 9 is 5V. Thus, for example, there was a need to provide a level shift circuit for level shifting the external voltage to the internal voltage, and level shifting the internal voltage to the external voltage in the internal flash memory.
FIG. 24 is a circuit diagram illustrating an embodiment of a level shift circuit according to the prior art. As shown in FIG. 24, the level shift circuit of the prior art embodiment comprises (1) a latch 10 configured by two inverters 11 and 12 cascaded to each other in a ring shape, (2) an inverter 13 inverting the output data of the latch 10 and outputting the output data signal DOUT (VCC), (3) NMOS transistors 31 and 32 being turned on in response to a latch signal with a high level for indicating a latching operation, (4) an NMOS transistor 21 being turned on in response to the input data signal DIN (VDD) with a high level, (5) an inverter 14 inverting the input data signal DIN (VDD), and (6) an NMOS transistor 22 being turned on in response to the output data signal of the inverter 14 with a high level.
In this embodiment, the sign in the parentheses of the input data signal DIN (VDD) indicates that the high level is the power supply voltage VDD with a high level, and the sign in the parentheses of the output data signal DOUT (VCC) indicates that the high level is the power supply voltage VCC with a high level. Therefore, the level shift circuit is provided with a latch 10 to temporarily hold the input data signal DIN (VDD), level shifts from the voltage VDD to the voltage VCC, and outputs the voltage VCC accordingly. In an embodiment of the NAND type flash memory, in order to output the data signal to an external device, it is necessary to level shift the internal VDD level data signal of the page buffer 2 to the external VCC level data signal.